Digital VLSI Chip Design with Cadence & Synopsys CAD Tools - 10-Part Guide for ASIC Engineers (Paperback 2009) | Learn IC Design for FPGA & Microprocessor Applications

I wanted to implement a test chip with custom-design standard cell library elements. I wanted to take an RTL design and perform synthesis, backend (place and route), and top-level chip assembly (with other custom components) using a 0.13 um technology and an accompanying standard cell library. My background prior to reading this book was exclusively custom chip design, though I was familiar with HDL coding (for FPGAs).Going through this book allowed me to learn the digital ASIC design flow, and provided enough details for me to figure out how to incorporate my own custom-designed standard cells, which required some hacking and/or modifications to the standard design flow. As you read through this book, there will be plenty of areas of confusion, and the sample scripts will not work without modification to your specific design software setup. However, I gave the book five stars based on the relative value it provides over reading the user manuals of the software tools individually or searching the web.P.S. the test chip worked!